Register field size:
Bits needed for register field = log₂(N)
where N = number of registers in the architecture

Maximum instructions encodable:
Max instructions = 2^(opcode bits)

Immediate value range (k-bit signed):
Range = −2^(k−1) to +2^(k−1) − 1

Instruction field constraint:
opcode bits + Σ(register field bits) + immediate bits = total instruction width

Effective Address calculations:
Direct: EA = address field
Indirect: EA = Memory[address field]
Register: EA = contents of register (no memory access)
Register Indirect: EA = Memory[Register]
Base + Offset: EA = Base_Register + Displacement
Indexed: EA = Index_Register + Base_address
PC-Relative: EA = PC + Offset

Sequential execution time:
T_seq = n × k × t_c
(n = instructions, k = stages, t_c = clock cycle time)

Pipelined execution time:
T_pipe = (k + n − 1) × t_c

Pipeline Speedup:
S = T_seq / T_pipe = (n × k) / (k + n − 1)
As n → ∞: S → k

Pipeline Efficiency:
E = S / k = n / (k + n − 1)
As n → ∞: E → 1 (100%)

Throughput:
TP = n / T_pipe = n / ((k + n − 1) × t_c)
As n → ∞: TP → 1 / t_c (instructions per second)

Clock cycle time (limited by slowest stage):
t_c = max(t_1, t_2, …, t_k) + t_latch
(t_latch = pipeline register overhead)

Effective CPI with stalls:
CPI_eff = 1 + Stall_cycles_per_instruction

CPI with data hazards (no forwarding):
CPI_eff = 1 + (hazard_frequency × stalls_per_hazard)

CPI with branch prediction:
CPI_eff = 1 + (branch_frequency × misprediction_rate × branch_penalty)

RAW stall cycles (no forwarding, 5-stage pipeline):
Consecutive instructions (i, i+1): 2 stalls
Instructions (i, i+2): 1 stall
Instructions (i, i+3+): 0 stalls

Load-use stall (with forwarding):
LW followed immediately by consumer: always 1 stall (forwarding cannot resolve)

Cache address breakdown:
Offset bits = log₂(block_size_in_bytes)
Index bits = log₂(number_of_sets)
Tag bits = physical_address_bits − index_bits − offset_bits
Verification: Tag + Index + Offset = Physical address bits ✓

Cache dimensions:
Number of sets = Cache_size / (block_size × associativity)
Number of blocks = Cache_size / block_size
Total cache lines = number_of_sets × associativity

Cache size (total including metadata):
Physical_data_size = number_of_lines × block_size
Overhead per line = tag_bits + valid_bit (+ dirty_bit for write-back)

Direct mapped — cache line for memory block b:
Cache line = b mod (number of cache lines)

Set-associative — set for memory block b:
Set number = b mod (number of sets)

AMAT — single level cache:
AMAT = Hit_time + (Miss_rate × Miss_penalty)

AMAT — two level cache:
AMAT = L1_Hit_time + L1_Miss_rate × (L2_Hit_time + L2_Miss_rate × Mem_time)

Global miss rate:
Global_miss_rate = L1_miss_rate × L2_local_miss_rate

Hit rate from miss rate:
Hit_rate = 1 − Miss_rate

Memory chip organisation:
Chips for bit extension = CPU_data_width / chip_data_width
Chips for word extension = total_memory / chip_capacity
Total chips = chips_bit_extension × chips_word_extension

Address lines:
Total address lines from CPU = log₂(total_memory / word_size_bytes)
Address lines to each chip = log₂(chip_locations)
Chip select lines = log₂(chips_word_extension)

Bus bandwidth:
Bandwidth = bus_width_bytes × bus_clock_frequency

Virtual memory — address breakdown:
Page_offset_bits = log₂(page_size_in_bytes)
VPN_bits = virtual_address_bits − page_offset_bits
Number_of_virtual_pages = 2^VPN_bits

Physical address:
PFN_bits = physical_address_bits − page_offset_bits
Number_of_physical_frames = 2^PFN_bits

Page table size (single level):
Page_table_size = Number_of_virtual_pages × PTE_size_bytes

EMAT with TLB:
EMAT = TLB_hit_rate × (TLB_time + Mem_access_time)
+ TLB_miss_rate × (TLB_time + Page_table_time + Mem_access_time)

Simplified:
EMAT = TLB_time + (TLB_miss_rate × Page_table_walk_time) + Mem_access_time

DRAM refresh overhead:
Refresh_time = Rows × Row_refresh_time
Overhead% = (Refresh_time / Refresh_period) × 100%

Polling overhead (CPU fraction):
CPU_fraction = (Poll_frequency × Cycles_per_poll) / CPU_clock_speed

Interrupt-driven I/O overhead:
Interrupts_per_second = Data_rate / Transfer_unit_size
CPU_cycles_per_second = Interrupts_per_second × Cycles_per_interrupt
CPU_fraction = CPU_cycles_per_second / CPU_clock_speed

DMA transfer time:
DMA_transfer_time ≈ Data_size / Device_transfer_rate
CPU_overhead = 1 start_interrupt + 1 end_interrupt (≈ negligible)

Cycle stealing — CPU slowdown:
If DMA steals 1 cycle every k CPU cycles:
CPU_speed_fraction = (k − 1) / k

Bus transfer time:
Transfer_time = Arbitration_time + Address_time + Data_size / Bus_bandwidth

Interrupt vector address:
IVT_entry_address = IVT_base + (Interrupt_type × Entry_size_bytes)

Two’s complement range (n bits):
Min = −2^(n−1), Max = +2^(n−1) − 1

Two’s complement negation:
−X = invert_all_bits(X) + 1
−X = 2^n − X (modular arithmetic)

Overflow detection (two’s complement addition):
Overflow = Carry_into_MSB ⊕ Carry_out_of_MSB
Overflow if: (+) + (+) = (−) result, OR (−) + (−) = (+) result

Sign extension (m bits to n bits, n > m):
Fill (n − m) MSBs with the sign bit of the m-bit number

Arithmetic right shift (divide by 2 for signed):
Shift right 1: MSB stays same (sign extended), same as ÷ 2 (round toward −∞)

Ripple carry adder delay:
T_RCA = n × t_FA
(n = bits, t_FA = full adder delay)

Carry lookahead — generate and propagate:
G_i = A_i AND B_i
P_i = A_i XOR B_i
C_{i+1} = G_i + P_i × C_i
T_CLA = O(log n)

IEEE 754 Single Precision (32-bit):
Value = (−1)^S × 1.M × 2^(E − 127)
Format: | S(1) | E(8) | M(23) |
Bias = 127 = 2^(8−1) − 1
Exponent range: −126 to +127 (E = 1 to 254); E=0 → denormal; E=255 → ±∞ or NaN

IEEE 754 Double Precision (64-bit):
Value = (−1)^S × 1.M × 2^(E − 1023)
Format: | S(1) | E(11) | M(52) |
Bias = 1023

Conversion: Decimal → IEEE 754 Single:
1. Determine S (sign)
2. Convert |value| to binary
3. Normalise: 1.xxx × 2^n
4. Stored E = n + 127
5. M = fractional bits after the “1.” (pad with zeros to 23 bits)

Booth’s Algorithm — bit pair decision table:
Q_i Q_{i−1} Operation
0 0 No operation
0 1 Add multiplicand
1 0 Subtract multiplicand
1 1 No operation
(followed by arithmetic right shift each step)