Instruction Set Architecture (ISA)
RISC vs CISC, Addressing Modes, Instruction Formats & Machine Code Encoding — GATE CS Notes
Last updated: April 2026 | GATE CS syllabus aligned
Key Takeaways
- The ISA is the interface between hardware and software — it defines what operations the CPU can perform and how operands are specified
- RISC architectures use fixed-length, simple instructions with a load/store model; CISC uses variable-length, complex instructions that can access memory directly
- Addressing modes determine how the effective address of an operand is computed — GATE tests all 7 major modes
- Instruction format divides the bit pattern of an instruction into opcode, register fields, and address/immediate fields
- For N registers, each register field in an instruction needs log₂(N) bits
- Endianness (big vs little) determines how multi-byte values are laid out in memory — a frequent source of confusion in GATE MCQs
- The number of instructions an ISA can support = 2^(opcode bits), minus any encoding reserved for other purposes
1. What Is an Instruction Set Architecture?
Every time you write a line of code, a compiler eventually translates it into a sequence of machine instructions. The ISA is the rulebook that defines what those instructions look like, what operations they can perform, and how they communicate with memory and registers. It sits at the boundary between hardware and software — hardware designers implement the ISA in silicon, and compilers generate code that uses it.
The ISA specifies:
- Instruction set: the complete list of operations the CPU can execute (ADD, SUB, LOAD, STORE, BRANCH, etc.)
- Data types: integers, floating-point numbers, characters, and their widths (8-bit, 32-bit, 64-bit)
- Registers: how many general-purpose registers exist, their width, and any special-purpose registers (PC, SP, flags)
- Addressing modes: how operand locations are specified in an instruction
- Memory model: byte-addressable vs word-addressable, endianness, alignment requirements
- Instruction encoding: how instructions are represented as binary bit patterns
Notice that the ISA does not say how fast instructions run, how many pipeline stages exist, or how large the cache is. Those are Organisation concerns. The same ISA (e.g., x86) can be implemented with radically different organisation — that is how Intel and AMD ship different hardware that runs the same software.
| ISA Concern (Architecture) | Organisation Concern |
|---|---|
| How many registers does the programmer see? | How many physical registers does the CPU actually have? (register renaming) |
| What instruction ADD Rd, Rs1, Rs2 does | How many clock cycles does ADD take? Is the ALU pipelined? |
| What addressing modes are supported | How is the effective address computed in hardware? |
| What the instruction encoding looks like | How the decoder parses that encoding at GHz speeds |
2. RISC vs CISC — Design Philosophy & Differences
In the 1970s and 80s, two competing philosophies emerged about how to design an ISA. The debate shaped modern computing, and GATE tests it directly almost every year.
CISC — Complex Instruction Set Computer
The guiding idea behind CISC was to close the “semantic gap” between high-level languages and machine code. If the hardware could execute a single instruction that did what a loop or procedure call does, then the compiler would be simpler and programs would be shorter. The x86 architecture (Intel, AMD) is the most widely used CISC ISA today.
RISC — Reduced Instruction Set Computer
Research in the 1980s at Stanford and Berkeley showed that despite having complex instructions, CISC processors spent 80% of their execution time on just 20% of their instruction set — and that 20% was simple. The insight: build a CPU optimised for simple instructions, run them fast in a pipeline, and let the compiler handle complexity. ARM (smartphones), MIPS (networking, GATE reference architecture), and RISC-V are RISC ISAs.
| Feature | RISC | CISC |
|---|---|---|
| Instruction set size | Small (50–200 instructions) | Large (300–1000+ instructions) |
| Instruction length | Fixed (e.g., always 32 bits) | Variable (1–15 bytes in x86) |
| Instruction complexity | Simple, one operation per instruction | Can perform multiple operations |
| Clock cycles per instruction (CPI) | ~1 (ideal) | 1–15+ (varies) |
| Memory access | Load/Store only — ALU ops use registers | ALU ops can directly access memory |
| Number of registers | Many (32 is typical) | Few (x86 has 8 general-purpose in 32-bit mode) |
| Addressing modes | Few, simple | Many, complex |
| Pipelining | Easy — fixed length helps decode | Harder — variable length complicates decode |
| Code size | Larger (more instructions needed) | Smaller (one instruction does more) |
| Compiler responsibility | High — compiler must optimise aggressively | Lower — hardware does more |
| Examples | MIPS, ARM, RISC-V, SPARC | x86, x86-64, VAX |
GATE often asks: “Which of the following is a characteristic of RISC?” The answer is always fixed-length instructions, load/store architecture, large register file, simple addressing modes, high CPI suitability for pipelining. CISC is characterised by variable-length instructions, memory-to-memory operations, and complex addressing modes.
3. Instruction Formats
An instruction is a binary pattern the CPU fetches from memory. The ISA defines how to break that pattern into fields — each field has a specific meaning.
Fields in a Typical Instruction
| Field | Purpose | Size (example: 32-bit MIPS) |
|---|---|---|
| Opcode | Identifies the operation (ADD, SUB, LOAD…) | 6 bits → 2⁶ = 64 possible R-type ops |
| rs (source 1) | First source register | 5 bits → 32 registers |
| rt (source 2 / dest) | Second source or destination register | 5 bits |
| rd (destination) | Destination register (R-type) | 5 bits |
| shamt | Shift amount (for shift instructions) | 5 bits |
| funct | Further specifies operation within an opcode group | 6 bits |
| Immediate | Constant value or address offset (I-type) | 16 bits |
MIPS Instruction Types (32-bit)
| opcode (6) | rs (5) | rt (5) | rd (5) | shamt (5) | funct (6) |
Example: ADD $t0, $t1, $t2 — adds $t1 and $t2, stores in $t0
I-Type (Immediate): used for loads, stores, branches
| opcode (6) | rs (5) | rt (5) | immediate (16) |
Example: LW $t0, 100($t1) — load word from address ($t1 + 100)
J-Type (Jump): used for unconditional jumps
| opcode (6) | target address (26) |
Example: J 0x00400020 — jump to address
Key Formula: Instruction Encoding
Bits needed to address N registers: log₂(N) bits
Max immediate value (signed, k bits): −2^(k−1) to 2^(k−1) − 1
Max immediate value (unsigned, k bits): 0 to 2^k − 1
Expanding Opcode Technique
When you want more instructions than a fixed opcode field allows, you use an expanding opcode scheme. Short opcodes are used for the most common 2-operand instructions; the remaining encoding space is reassigned with a longer opcode for 1-operand or 0-operand instructions.
Example: 16-bit instruction with 4-bit opcode, 2 register fields (4 bits each).
- Normal: 4-bit opcode → 16 possible instructions, each with two 4-bit register fields
- If we reserve opcode = 1111 for a 2nd tier: 8-bit opcode → 16 more single-register instructions
- If we reserve 1111 1111 for a 3rd tier: 12-bit opcode → 16 zero-operand instructions
4. Addressing Modes — All 7 Types Explained
An addressing mode defines how the CPU computes the effective address (EA) of an operand. GATE tests all seven modes, often through numerical questions where you must compute the EA given register values and instruction fields.
| Mode | Effective Address / Operand | Notation | Example Use |
|---|---|---|---|
| Immediate | Operand = value in instruction itself (no memory access) | ADD R1, #5 | Loading constants, loop counters |
| Register | Operand = contents of register (no memory access) | ADD R1, R2 | Most ALU operations in RISC |
| Direct (Absolute) | EA = address field in instruction; Operand = Memory[EA] | LOAD R1, 2000 | Accessing global variables |
| Indirect | EA = Memory[address field]; Operand = Memory[EA] | LOAD R1, (2000) | Pointer dereferencing |
| Register Indirect | EA = contents of register; Operand = Memory[Reg] | LOAD R1, (R2) | Pointer access via register |
| Base + Offset (Displacement) | EA = Base_Reg + displacement; Operand = Memory[EA] | LOAD R1, 100(R2) | Struct fields, stack frames |
| Indexed | EA = Index_Reg + base_address; Operand = Memory[EA] | LOAD R1, 2000(R3) | Array element access |
Immediate: 0 (operand in instruction)
Register: 0 (operand in register)
Direct: 1 (one memory read)
Indirect: 2 (read address, then read operand)
Register Indirect: 1 (register holds address, one memory read)
Base+Offset: 1 (EA computed from register + displacement, one memory read)
Indexed: 1 (EA computed, one memory read)
5. Endianness — Big vs Little Endian
When a multi-byte value (like a 32-bit integer) is stored in memory, we need a convention for which byte goes to which address. This is endianness.
| Endianness | Most Significant Byte at | Example: 0x12345678 in addresses 100–103 | Used By |
|---|---|---|---|
| Big-Endian | Lowest address | 100:0x12, 101:0x34, 102:0x56, 103:0x78 | MIPS, SPARC, network protocols (TCP/IP) |
| Little-Endian | Highest address | 100:0x78, 101:0x56, 102:0x34, 103:0x12 | x86, x86-64, ARM (configurable) |
Network byte order is big-endian. When a little-endian x86 machine sends data over a network, the system must call htons() (host-to-network short) to swap bytes. This connection between COA endianness and Computer Networks is a favourite GATE cross-topic question.
6. GATE-Level Worked Examples
Example 1 — Instruction Format Encoding (GATE 2019 style)
Problem: A CPU has a 32-bit instruction format. The opcode is 8 bits. There are 3 register fields and one 8-bit immediate field. How many registers can this CPU support?
Total bits = 32
Opcode = 8 bits, Immediate = 8 bits
Remaining for register fields = 32 − 8 − 8 = 16 bits
Each register field = 16 / 3 ≈ 5.33 — but bits must be integers.
If we take 5 bits per register field → 3 × 5 = 15 bits used → 1 bit unaccounted (padding or reserved)
Number of registers = 2⁵ = 32 registers
Example 2 — Effective Address Calculation (GATE 2021 style)
Problem: An instruction uses Base+Offset addressing. The base register R1 = 3000, the displacement in the instruction = 200, and the program counter PC = 5000. What is the effective address?
Base+Offset: EA = Base_Register + Displacement
EA = R1 + displacement = 3000 + 200 = 3200
(Note: PC is irrelevant here — PC-relative addressing would use PC + displacement, which would give 5200. Read the mode carefully.)
Example 3 — Expanding Opcode (GATE 2018 style)
Problem: A 16-bit instruction has a 4-bit opcode, and each instruction has two 6-bit register fields. Using an expanding opcode scheme, how many 1-operand instructions can be encoded if 14 out of 16 base opcodes are used for 2-operand instructions?
Total 4-bit opcodes = 16
Used for 2-operand: 14 → Remaining: 2 opcodes = 0b1110 and 0b1111
Each unused 4-bit opcode extends with the first 6-bit register field as additional opcode bits:
Extended opcode space per unused code = 2⁶ = 64
But one of those 6-bit patterns must be reserved for further expansion (if needed); else all 64 available.
1-operand instructions (using both extended patterns) = 2 × 64 = 128 instructions
Each uses only one 6-bit register field (the second field is part of the opcode)
7. Common Mistakes
-
Confusing ISA with Organisation
The number of pipeline stages, cache size, and clock speed are organisation details — not part of the ISA. The ISA only defines what the programmer sees. GATE questions sometimes give organisation details as distractors when asking about ISA. -
Confusing Indirect and Register Indirect addressing
In Indirect mode, the instruction contains a memory address whose contents give the effective address — two memory accesses total. In Register Indirect, a register holds the effective address — only one memory access. The key difference: where the pointer lives (memory vs register). -
Getting endianness wrong
Big-endian stores the MSB at the lowest address, which is the “natural” reading order (left to right). Students sometimes confuse this and store MSB at the highest address. Remember: big-endian = big end first at low address. -
Using integer division for register field bits
If 16 bits are shared among 3 register fields, you cannot use 16/3 ≈ 5.33 bits. Each field must be a whole number of bits. Always check whether the problem specifies the field size, or whether you are deriving it from the number of registers. -
Claiming RISC always has lower CPI than CISC
RISC aims for CPI close to 1 per instruction. But RISC programs may need more instructions to do the same job as one CISC instruction. The actual performance comparison depends on the product of instruction count × CPI × clock period — not CPI alone.
8. Frequently Asked Questions
What is the difference between RISC and CISC?
RISC (Reduced Instruction Set Computer) uses a small set of fixed-length, simple instructions with load/store memory access and many registers. CISC (Complex Instruction Set Computer) has a large set of variable-length instructions where individual instructions can directly access memory and perform multi-step operations. RISC is designed to be pipeline-friendly; CISC prioritises code density.
What are the different addressing modes in computer organisation?
The seven main addressing modes are: Immediate (operand in instruction), Register (operand in register), Direct (instruction holds memory address), Indirect (instruction holds address of address — two memory accesses), Register Indirect (register holds address — one memory access), Base+Offset (EA = base register + displacement), and Indexed (EA = index register + base address). Each mode trades off flexibility, speed, and instruction size.
How many bits are needed to represent N registers in an instruction?
You need ⌈log₂(N)⌉ bits. For 32 registers: log₂(32) = 5 bits. For 64 registers: log₂(64) = 6 bits. For 16 registers: log₂(16) = 4 bits. This formula directly determines how large the register fields in your instruction format must be.
What is the difference between little-endian and big-endian?
Big-endian stores the most significant byte (MSB) at the lowest memory address — the byte that would be written first if you read the number left to right. Little-endian stores the least significant byte (LSB) at the lowest address. x86 processors are little-endian; the internet (TCP/IP) uses big-endian (network byte order). The difference matters when interpreting raw memory dumps or writing network code.