RTL Design Engineer Role – HCLTech - HCLTech

RTL Design Engineer | 5-12 Years We are seeking an RTL Design Engineer with 5-12 years of ASIC/SoC design experience to drive the development of high-performance digital designs from architecture to implementation. Key Requirements: Strong experience in RTL design using Verilog/SystemVerilog or VHDL Hands-on experience in ASIC/SoC development Strong understanding of digital design concepts, including combinational logic, sequential logic, and FSMs Experience in functional verification and RTL d…

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