Sequential Circuits & Flip-Flops
From latches to synchronous counters – understand how digital circuits store and sequence state. Master excitation tables, characteristic equations, and counter design for GATE CS.
Last updated: April 2026 | GATE CS 2024-2026 syllabus
Key Takeaways
- Sequential circuits have memory – output depends on current inputs AND stored state. They require flip-flops or latches.
- Latch: level-sensitive (output tracks input while enable is high). Flip-flop: edge-triggered (output changes only at clock edge).
- SR FF: forbidden state when S=R=1. D FF: Q(t+1) = D. JK FF: toggles when J=K=1. T FF: toggles when T=1.
- Excitation table: given Q(t) and Q(t+1), find required inputs – used in sequential circuit design.
- Synchronous counter: all FFs clocked together, faster, no glitches. Asynchronous (ripple) counter: FFs clocked in series, simpler but slower.
- Mod-N counter: cycles through N states. Design using synchronous method (state table + K-maps) or asynchronous reset method.
- Shift registers: SISO, SIPO, PISO, PIPO – used for serial/parallel data conversion and data storage.
1. Sequential Circuits – Overview
A sequential circuit is a digital circuit whose output depends on both the current inputs and the current stored state. It has memory elements (flip-flops or latches) that hold state between clock cycles.
Output: Z = g(inputs, current state) [Mealy] or Z = h(current state) [Moore]
Sequential circuits are classified as:
- Synchronous: State changes occur only at clock edges. All flip-flops share the same clock. Predictable and glitch-free.
- Asynchronous: State changes occur immediately when inputs change. No shared clock. Faster but harder to design and prone to hazards.
2. Latches
A latch is a level-sensitive bistable element – it stores one bit and can change state while the enable signal is asserted.
2.1 SR Latch (NAND-based)
S=1, R=0: Q = 1 (Set)
S=0, R=1: Q = 0 (Reset)
S=0, R=0: Q = Q (Hold – no change)
S=1, R=1: Q = undefined (Forbidden state – both outputs try to be 1)
| S | R | Q(t+1) | Q'(t+1) | Comment |
|---|---|---|---|---|
| 0 | 0 | Q(t) | Q'(t) | Hold |
| 0 | 1 | 0 | 1 | Reset |
| 1 | 0 | 1 | 0 | Set |
| 1 | 1 | X | X | Forbidden |
2.2 D Latch (Data Latch)
The D latch eliminates the forbidden state by tying R = S'. The enable input EN controls whether D is captured.
When EN = 0: Q(t+1) = Q(t) (holds last value when EN went low)
The D latch is the basis for the D flip-flop (master-slave or edge-triggered).
3. Flip-Flops
A flip-flop is an edge-triggered bistable element – it samples inputs at the rising (or falling) clock edge and ignores input changes at all other times.
3.1 SR Flip-Flop
| S | R | Q(t+1) |
|---|---|---|
| 0 | 0 | Q(t) (Hold) |
| 0 | 1 | 0 (Reset) |
| 1 | 0 | 1 (Set) |
| 1 | 1 | X (Forbidden) |
3.2 D Flip-Flop
The simplest and most widely used flip-flop in synchronous design. The output after the clock edge equals the data input before the edge. No forbidden state.
| D | Q(t+1) |
|---|---|
| 0 | 0 |
| 1 | 1 |
3.3 JK Flip-Flop
The JK flip-flop resolves the SR forbidden state: when J=K=1, the output toggles (Q(t+1) = Q'(t)).
| J | K | Q(t+1) | Operation |
|---|---|---|---|
| 0 | 0 | Q(t) | Hold |
| 0 | 1 | 0 | Reset |
| 1 | 0 | 1 | Set |
| 1 | 1 | Q'(t) | Toggle |
3.4 T Flip-Flop (Toggle)
The T flip-flop is a special case of JK with J=K=T. When T=1, it toggles. When T=0, it holds.
| T | Q(t+1) | Operation |
|---|---|---|
| 0 | Q(t) | Hold |
| 1 | Q'(t) | Toggle |
T flip-flops are ideal for counters because a binary counter simply toggles the LSB every clock cycle, the next bit every 2 cycles, and so on.
Flip-Flop Comparison Summary
| Type | Characteristic Equation | Forbidden State | Best Used For |
|---|---|---|---|
| SR | Q+ = S + R'Q, SR=0 | Yes (S=R=1) | Set/Reset control |
| D | Q+ = D | None | Registers, synchronous design |
| JK | Q+ = JQ' + K'Q | None (toggles) | Versatile, all operations |
| T | Q+ = T ⊕ Q | None | Counters, frequency division |
4. Excitation Tables and Flip-Flop Conversions
An excitation table answers: given the current state Q(t) and the desired next state Q(t+1), what inputs are required?
This is used in sequential circuit design: you know the desired state sequence and need to find the flip-flop input equations (the combinational logic that drives each FF input).
Excitation Tables for All Four Flip-Flops
| Q(t) | Q(t+1) | SR: S R | D | JK: J K | T |
|---|---|---|---|---|---|
| 0 | 0 | 0 X | 0 | 0 X | 0 |
| 0 | 1 | 1 0 | 1 | 1 X | 1 |
| 1 | 0 | 0 1 | 0 | X 1 | 1 |
| 1 | 1 | X 0 | 1 | X 0 | 0 |
X = dont-care. For D FF, the input equals the desired next state directly – the simplest excitation.
Flip-Flop Conversion (JK to D, D to T, etc.)
To convert from one FF type to another:
- Write the characteristic equation of the target FF (the one you want to build).
- Use the excitation table of the available FF to find what its inputs must be for each state transition.
- Use K-maps to simplify the input equations in terms of the state variables.
Example – D FF from JK FF: D FF requires Q(t+1) = D. JK excitation says: to go 0→0 need J=0,K=X; to go 0→1 need J=1,K=X; to go 1→0 need J=X,K=1; to go 1→1 need J=X,K=0. Since D = Q(t+1), J = D and K = D'.
5. Registers and Shift Registers
A register is a group of flip-flops that store multiple bits of data. A shift register shifts data left or right by one bit per clock cycle.
Types of Shift Registers
| Type | Full Name | Input | Output | Use |
|---|---|---|---|---|
| SISO | Serial In, Serial Out | 1-bit serial | 1-bit serial | Delay line, data pipeline |
| SIPO | Serial In, Parallel Out | 1-bit serial | n-bit parallel | Serial-to-parallel conversion |
| PISO | Parallel In, Serial Out | n-bit parallel | 1-bit serial | Parallel-to-serial conversion |
| PIPO | Parallel In, Parallel Out | n-bit parallel | n-bit parallel | Buffer register, data storage |
Shift Register Arithmetic
Right shift by 1: Equivalent to dividing by 2 (arithmetic right shift preserves sign bit)
Ring Counter and Johnson Counter
- Ring counter: n-bit shift register with output connected back to input. Circulates a single 1 through n states. Mod-n operation. n FFs, n states.
- Johnson counter (Twisted Ring): Q' fed back to input instead of Q. n FFs give 2n states. Generates a Gray code sequence.
6. Counters
6.1 Asynchronous (Ripple) Counter
In a ripple counter, each FF is clocked by the Q output of the previous FF. Only the first FF is driven by the external clock.
- 2-bit ripple counter: FF0 toggles every clock; FF1 toggles when Q0 goes from 1→0 (negative edge). Counts 00 → 01 → 10 → 11 → 00.
- Propagation delay: Each FF introduces its own delay. Total delay = n × tFF. For high-frequency operation, this cumulative delay becomes a problem.
6.2 Synchronous Counter
All flip-flops share the same clock signal. Inputs to each FF are controlled by combinational logic that ensures the correct state sequence.
T0 = 1 (FF0 toggles every clock)
T1 = Q0 (FF1 toggles when Q0=1)
T2 = Q0Q1 (FF2 toggles when Q0=Q1=1)
T3 = Q0Q1Q2 (FF3 toggles when Q0=Q1=Q2=1)
All FFs change simultaneously – no ripple delay. But carries must be computed by the combinational logic, which can be complex for wide counters.
6.3 Mod-N Counter Design
A mod-N counter cycles through exactly N states (typically 0 to N-1) and resets.
Method 1 – Synchronous Design (most reliable for GATE questions):
- Write the state table (N states, next state = (current state + 1) mod N).
- Fill excitation table for chosen FF type.
- Use K-maps to derive input equations (treat unused states as dont-cares).
- Implement the combinational logic.
Method 2 – Asynchronous Reset:
- Use a natural binary counter of size 2k where 2k ≥ N.
- Detect state N with a NAND gate: inputs are all the bits that are 1 in binary N.
- Connect the NAND output to CLR (active-low clear) of all FFs.
- The counter briefly enters state N, then immediately resets to 0.
Note: State 6 appears momentarily – this is acceptable in most applications but not for glitch-sensitive systems.
| Mod-N | FFs needed | Detection logic for async reset |
|---|---|---|
| Mod-3 | 2 | NAND(Q1, Q0) [state 3 = 11] |
| Mod-5 | 3 | NAND(Q2, Q0) [state 5 = 101] |
| Mod-6 | 3 | NAND(Q2, Q1) [state 6 = 110] |
| Mod-10 | 4 | NAND(Q3, Q1) [state 10 = 1010] |
| Mod-12 | 4 | NAND(Q3, Q2) [state 12 = 1100] |
7. GATE CS Solved Examples
Example 1 – Excitation Table Application (GATE CS 2018)
Question: A 2-bit synchronous counter uses two JK flip-flops. Design the counter to count: 00 → 01 → 11 → 10 → 00 (Gray code sequence). Find the JK inputs for each FF.
State table:
| Present State Q1Q0 | Next State Q1+Q0+ | J1 K1 | J0 K0 |
|---|---|---|---|
| 0 0 | 0 1 | 0 X | 1 X |
| 0 1 | 1 1 | 1 X | X 0 |
| 1 1 | 1 0 | X 0 | X 1 |
| 1 0 | 0 0 | X 1 | 0 X |
K-map for J1 (rows are Q1Q0 in Gray code order 00,01,11,10):
- Q1=0, Q0=0: J1=0
- Q1=0, Q0=1: J1=1
- Q1=1, Q0=1: J1=X
- Q1=1, Q0=0: J1=X
Group: {Q0=1 cells} where J1=1 and X→ J1 = Q0
K-map for K1:
- Q1=0, Q0=0: K1=X; Q1=0, Q0=1: K1=X; Q1=1, Q0=1: K1=0; Q1=1, Q0=0: K1=1
Only Q0=0,Q1=1 forces K1=1 → K1 = Q0'
Note: J1 = K1' = Q0 means both J and K are determined by Q0, making this a D-like behavior for FF1 where D = Q0.
Example 2 – Ripple Counter Timing (GATE CS 2015)
Question: A 4-bit ripple counter uses T flip-flops each with propagation delay 5 ns. The clock frequency is 50 MHz. Is the counter reliable?
Solution:
- Clock period = 1 / 50 MHz = 20 ns
- Maximum ripple delay = 4 × 5 ns = 20 ns
- The ripple delay equals the clock period – the MSB just barely settles before the next edge. In practice, with setup time requirements, this counter would fail.
Example 3 – Mod-6 Counter using JK FFs (GATE CS 2020 style)
Question: Design a synchronous mod-6 counter using JK flip-flops. Write the state table and find J, K equations.
State table (3 FFs: Q2Q1Q0, states 6-7 are unused/dont-care):
| State | Q2Q1Q0 | Q2+Q1+Q0+ | J2 K2 | J1 K1 | J0 K0 |
|---|---|---|---|---|---|
| 0 | 000 | 001 | 0 X | 0 X | 1 X |
| 1 | 001 | 010 | 0 X | 1 X | X 1 |
| 2 | 010 | 011 | 0 X | X 0 | 1 X |
| 3 | 011 | 100 | 1 X | X 1 | X 1 |
| 4 | 100 | 101 | X 0 | 0 X | 1 X |
| 5 | 101 | 000 | X 1 | 0 X | X 1 |
| 6 | 110 | XXX | X X | X X | X X |
| 7 | 111 | XXX | X X | X X | X X |
After K-map simplification (using states 6-7 as dont-cares):
J1 = Q0 K1 = Q0
J0 = Q2' K0 = 1
8. Common Mistakes
Mistake 1 – Confusing latch and flip-flop triggering
Error: Saying a D flip-flop outputs D whenever D changes.
Root cause: Confusing the D latch (level-sensitive) with the D flip-flop (edge-triggered).
Fix: A D FF captures D only at the clock edge. Between edges, Q remains constant regardless of D changes. A D latch is transparent when EN=1.
Mistake 2 – Using SR FF with S=R=1
Error: Applying S=R=1 to an SR flip-flop and expecting a defined output.
Root cause: Not recognising the forbidden state.
Fix: Add constraint SR=0 to all SR FF designs. Use JK FF if toggling is needed – it handles J=K=1 by toggling.
Mistake 3 – Wrong excitation table lookup
Error: Confusing the truth table (what output do I get for given inputs?) with the excitation table (what inputs do I need to achieve a desired transition?).
Root cause: The two tables look similar but answer different questions.
Fix: Excitation table rows are (Q, Q+) pairs. For each row in your state table, look up the required FF inputs. Then use K-maps on those FF inputs.
Mistake 4 – Mod-N counter state detection error
Error: Detecting the wrong state for the asynchronous reset method. For mod-6, detecting state 7 (111) instead of state 6 (110).
Root cause: Using the highest unused state (2k-1) instead of N.
Fix: The reset must trigger on state N (the first forbidden state after N-1). Convert N to binary and AND all the 1-bits. For mod-6: 6=110, AND Q2 and Q1 (not Q0).
Mistake 5 – Ripple counter frequency limit calculation
Error: Calculating the maximum clock frequency of a ripple counter as 1/tFF instead of 1/(n × tFF).
Root cause: Forgetting that all n flip-flops contribute to the worst-case delay.
Fix: The worst-case is when all bits toggle (e.g., 0111 → 1000). All n FFs must settle before the next clock edge. fmax = 1/(n × tFF + tsetup).
9. Frequently Asked Questions
What is the difference between a latch and a flip-flop?
A latch is level-sensitive – it changes output while the enable is asserted. A flip-flop is edge-triggered – it captures input only at the clock edge and holds the value until the next edge. Flip-flops are used in synchronous design because they provide predictable, clock-controlled state transitions.
What is an excitation table and how is it different from a truth table?
A truth table for a flip-flop shows Q(t+1) given Q(t) and inputs. An excitation table inverts this: given Q(t) and desired Q(t+1), it shows the required inputs. Excitation tables are used in sequential design to determine what combinational logic must drive each FF input to achieve the desired state sequence.
What is the difference between synchronous and asynchronous counters?
In a synchronous counter, all FFs share the same clock and change state simultaneously – faster, no glitches, but needs more complex input logic. In an asynchronous (ripple) counter, each FF is clocked by the previous FF output – simpler but slower due to cumulative propagation delays. For GATE CS, know both designs and their delay equations.
How do you design a mod-N counter?
Method 1 (synchronous): Write the N-state table, apply excitation table for chosen FF, simplify input equations with K-maps. Method 2 (asynchronous reset): Use a 2k-bit binary counter, detect state N with a NAND gate on the 1-bits of N, connect to CLR of all FFs. The counter briefly enters state N then resets – a glitch-reset approach.